Module csr 

Control and status registers, privilege levels, and trap causes.

These are the machine state an operating system owns and a user program cannot reach. They are addressed by number through csrr and csrw rather than mapped into memory, so that reaching them is a privilege check on one instruction instead of a check on every load and store.

Modules

irq

Interrupt request lines: which trit of the interrupt masks each device owns.

num

Register numbers accepted by csrr and csrw.

Structs

Csrs

The control and status registers.

Enums

Cause

Why a trap was taken.

Priv

Privilege level, held in one trit.

Functions

prelude

Assembler .equ lines naming every control register, cause and flag.