Crate ternaria_vm 

The reference interpreter.

A fetch, decode, execute loop written for clarity rather than speed. Later implementations, including the phase 7 JIT, are checked against it.

Machine state

• 27 registers numbered -13 to 13 (D-05). r0 reads as zero and discards writes.
• pc holds the tryte address of the instruction being executed. It advances by 3 trytes unless an instruction redirects it.
• Memory is passed in rather than owned, so one Cpu can run against different memories and state stays separable from storage.

Traps

Every abnormal condition raises a Trap carrying the pc that caused it. Arithmetic overflow traps rather than wrapping, uninitialised reads trap rather than returning zero, and undefined opcodes trap.

Wrapping arithmetic exists in ternaria-arith and can be exposed as separate opcodes if a program needs it.

Re-exports

pub use csr::Cause;

pub use csr::Csrs;

pub use csr::Priv;

pub use mmu::Access;

pub use mmu::Entry as PageEntry;

Modules

asm

A small text assembler.

csr

Control and status registers, privilege levels, and trap causes.

mmu

Address translation: trit-sliced page tables.

Structs

Cpu

The processor.

Halted

Result of a completed run.

Imm

A 12-trit immediate, +/-265,720.

Instruction

A decoded instruction.

Reg

An architectural register, numbered -13 through 13.

Enums

DecodeError

Why a word is not a valid instruction.

MemError

Something went wrong with a memory access.

Opcode

Every defined operation.

Trap

Something stopped execution.

Functions

assemble_and_load

Assembles source, loads it at at, and returns a Cpu ready to run.

load

Writes instructions into memory as consecutive words. at must be word-aligned.